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es_lpc3230 errata sheet lpc3230 rev. 9 ? 1 june 2011 errata sheet document information info content keywords lpc3230 errata abstract this errata sheet describes both the known functional problems and any deviations from the electrical specific ations known at t he release date of this document. each deviation is assigned a number and its history is tracked in a table.
es_lpc3230 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 1 june 2011 2 of 17 contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors es_lpc3230 errata sheet lpc3230 revision history rev date description 9 20110601 ? added usb.1. 8 20110201 ? added hsuart.1. 7 20100624 ? added dma.1. ? added nor.1. 6 20100318 ? added clarification regarding /01 revision ?a? parts. 5 20100205 ? the format of this errata sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? added ddr write set-up time.
es_lpc3230 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 1 june 2011 3 of 17 nxp semiconductors es_lpc3230 errata sheet lpc3230 1. product identification the lpc3230 devices typically have the following top-side marking: LPC3230FET296 xxxxxxx xxyywwr the last letter in the la st line (field ?r?) will identify the device revision. this errata sheet covers the following revisions of the lpc3230: [1] revision ?a? parts with and without the /01 suffix are identical. for example, LPC3230FET296 revision ?a? is identical to LPC3230FET296/01 revision ?a?. [2] does not apply to /01 parts. field ?yy? states the year the device was manufactured. field ?ww? states the week the device was manufactured during that year. 2. errata overview table 1. device revision table revision identifier (r) revision description ?a? [1] second device revision ?-? [2] initial devi ce revision table 2. functional problems table functional problems short description revision identifier detailed description dma.1 single burst dma memory -to-memory transfers have additional memory cycles when the dma source memory is on the emc bus. ?-?, ?a? section 3.1 on page 5 nor.1 when booting from nor fl ash, sdram devices will not release the data bus, preventing the lpc3230 from booting correctly ?-?, ?a? section 3.2 on page 7 ddr.2 ddr emc_d[15:0] to emc_dqs[1:0] data output set-up time, t su(q) , for mcu write to ddr provides limited timing margin ?-?, ?a? section 3.3 on page 8 ddr.1 ddr interface has > 1. 2 ns clock skew ?-?, ?a? section 3.4 on page 11 lcd.1 reduced bandwidth when lcd controller accesses ddr/sdram ?-? section 3.5 on page 11 rtc.1 an rtc match doesn't drive the onsw pin active (high). ?-?, ?a? section 3.6 on page 12 int.1 gpi_08 does not generate in interrupt signal. ?-? section 3.7 on page 12 mcpwm.1 input pins (mci0-2) on the motor control pwm peripheral are not functional ?-?, ?a? section 3.8 on page 13 hsuart.1 high speed uart receive fifo and status can freeze ?-?, ?a? section 3.9 on page 14 usb.1 usb host controller hangs on a dribble bit ?-?, ?a? section 3.10 on page 15
es_lpc3230 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 1 june 2011 4 of 17 nxp semiconductors es_lpc3230 errata sheet lpc3230 table 3. ac/dc deviations table ac/dc deviations short description revision identifier detailed description esd.1 weak esd protection on reset_n pin (pin m14) ?-? section 4.1 on page 15
es_lpc3230 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 1 june 2011 5 of 17 nxp semiconductors es_lpc3230 errata sheet lpc3230 3. functional problems detail 3.1 dma.1: single burs t dma memory-to-memory transfers have additional memory cycles when the dma source memory is on the emc bus introduction: the dma controller is an ahb master that can transfer blocks of data between peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory. in addition to tran sferring data between memories, a dma memory-to-memory flow can be used to transfer blocks of data to / from an fpga or external peripheral chip connected to an emc static memory chip select. when a memory, fpga or external peripheral chip does not s upport burst transfers (i.e. multiple reads for each active chip select or read strobe) the burst size for that memory-to-memory flow must be set for one transfer per burst. problem: when using memory-to-memory dma with the em c static chip select (emc_cs[x]_n) as the dma source and the dma channel source burst size is set fo r a single transfer (dmaccxcontrol:sbsize = 0) , each dma source read should be a single bus-wide access. the access should be similar to reading the emc_cs[x]_n static memory with an arm ldr instruction, as shown in figure 1 . note the emc signal timing for the read is controlled by the emcstaticx registers. in all example scope shots the emcstaticwaitx registers are set to the maximum value. however, the actual emc timing for the source dma read is a double wide chip select with a burst of two reads (notice how the address increments nea r the halfway point of ncs0 active), see figure 2 . the second data read during the burst is discarded, as the dma destination write (a lso to ncs0 in figure 2 ) following each read, always writes the first value read during the read burst. when the dma source address is set to auto-increment, the last dma read transfer will address the last address of t he source buffer and the last source buffer address +1. this behavior only happens during the read part of the dma transfer. memory-to-memory dma destination writes to the emc st atic chip select work as expected. fig 1. scope shot 1 - expected read timing
es_lpc3230 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 1 june 2011 6 of 17 nxp semiconductors es_lpc3230 errata sheet lpc3230 dma register values used in figure 2 : dmacconfig = 0x01 dmaccxsrcaddr = 0xe0000000; emc_cs0 dmaccxdestaddr = 0xe0000040; emc_cs0 dmaccxlli = 0x0 dmaccxcontrol = 0x0c480004; dest & src addrs increment, dest & src 32-bit; dburst & sburst size 1; transfer size 4 dmaccxconfig = 0x01 emcstaticconfig0 = 0x00000082; 32-bit width, byte lane state 1 results of this behavior: 1. dma reads from an external memory will have lower performa nce than a software read loop. the source read burst of two, to get one tran sfer, will significa ntly increase the time to complete all transfers in the memory-to-memory dma, therefore decreasing the overall throughput possible on the emc_csx_n static memory interface. 2. potential unintended consequence when the last dma read accesses the address beyond the dma source buffer address in t he fpga or external peripheral chip. this extra address is the seco nd access during the last dma source read. fig 2. scope shot 2 - actual read timing
es_lpc3230 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 1 june 2011 7 of 17 nxp semiconductors es_lpc3230 errata sheet lpc3230 work-around: when interfacing an external peripheral device that does not support burst mode access through the emc static memory interface the following work-arounds are recommended: 1. avoid using dma to transfer read blocks of data from the external device. instead use a software loop with ldr inst ruction to read blocks of data from the external device. 2. if dma can't be avoided, ensure there is at least one unused address between the highest address used for the external device dma data buffer and any status or control register in the device that will initiate any unwanted action just by reading from the register (i.e. clear an interrupt or status). 3.2 nor.1: when booting from no r flash, sdram d evices will not release the data bus, preventing th e lpc3230 from booting correctly introduction: in systems that use sdram and boot from nor flash, an issue can occur on system reset that will prevent the sdram devices from releasing the data bus. this will prevent normal operation of nor flash due to dat a bus contention and prevent the lpc3230 from booting correctly. this applies to systems using either single data rate (sdr) or double data rate (ddr) sdram devices. problem: if the lpc3230 is reset during an sdram a ccess, the sdram clock and clock enable will be immediately de-asserted. if the de-assertion occurs during the period of time the sdram is driving the data bus, the sdram will hold that state until th e next clock occurs at the sdram clock input when the clock en able is active. however, the lpc3230 won't deliver the clock and clock enables until software actually sets up the emc state to do this, so the sdram will remain in the data as sertion state on the data bus while the lpc3230 tries to boot. when the chip attempts to load boot code from nor fl ash after reset, the correct signals are asserted to the nor flash dev ice and the nor flash device places its data on the data bus. but if the sdram is still driving the bus, the nor flash device and sdram device are in contention and th e data will not be read correctly into the lpc3230. in this situation, the lpc3230 will fail to boot. work-around: since this issue only occurs with nor flash , using one of the other boot methods such as nand or spi flash boot is a good workaround for the issue. if booting from nor flash is a requirement, the simple circuit shown in figure 3 can be used to clear the sdram st ate at system rese t. this will not change the normal functioning of the lpc3230 emc or sdram operations. if sdram devices are also present on the 2nd sdram chip select, a sim ilar circuit will be needed for those devices using emc_cke1.
es_lpc3230 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 1 june 2011 8 of 17 nxp semiconductors es_lpc3230 errata sheet lpc3230 3.3 ddr.2: ddr emc_d[15:0] to emc_ dqs[1:0] data output set-up time, t su(q) , for mcu write to ddr prov ides limited timing margin remark: this affects both 1.8 v mobile and 2.5 v ddr sdram system implementations. introduction: ddr memory interface signal emc_ dqs[1:0] is source synchronous, defined to be driven by the mcu center aligned to the data emc_d[15:0] for wr ites, while driven by the ddr memory edge aligned to the emc_d[15:0] for re ads. the basic ddr write timing is shown in the data sheet fig 1. problem: for ddr writes the lpc3230 drives the emc_ dqs[1:0] earlier in the data valid window than center aligned. with the emc_clk at 133 mhz this produces a minimum set-up time between the emc_d[15:0] and emc_dqs[1:0] of 600 ps acro ss silicon process, voltage and temperature. test conditions are with the emc buffers set to fast slew rate driving fig 3. 128 mb ddr sdram example fig 4. basic ddr write timing command emc_d[15:0], emc_dqm[1:0] t dqsl t dqsh t dqss t h(q) emc_dqs[1:0] emc_clk 002aae437 write t su(q) t dsh t dss
es_lpc3230 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 1 june 2011 9 of 17 nxp semiconductors es_lpc3230 errata sheet lpc3230 2 inches of 50 ? transmission line and 10 pf load capacitance. ddr memories specify emc_d[15:0] to emc_dqs[1:0] set-up time minimum as 400 ps. this leaves 200 ps set-up time margin due to customer specific load and pcb layout implementation. see the lpc3220_30_40_50 data sheet for the complete range of ddr data output set-up time, t su(q) , and data output hold time t h(q) times. work-around: to get the most ddr set-up time margin, the following is recommended: 1. the ddr initialization software should set the sdramclk_ctrl register (0x4000 4068) sdram_pin_speed[3:1] bits = 0 (fast slew rate). this is for both 1.8 v mobile and 2.5 v ddr memories. 2. systems requiring 128 mb or less of ddr should be implemen ted using a single emc_dycsx_n for ddr. the single chip se lect system may be constructed with a single 16-bit wide ddr or two 8-bit wide ddr sdrams using up to the maximum supported 512 mbit ddr density. using two 8-bit wide ddrs will have less capacitive loading and facilitate simple point-to -point routing of emc_d[15:0] and emc_dqs[1:0] signals over using two 16-bit ddrs and two emc_dycsx banks. 3. series termination resistors are not neede d for the lpc3230 emc outputs. if series termination resistors are used they should be placed as close to the ddr emc_d[15:0] and emc_dqs[ 1:0] pins as possible. 4. if the data bus emc_d[15:0] is shared wit h additional devices (i.e., nor flash, buffers, etc.) the board should be routed with a daisy chain topology, where the lpc3230 is placed at one extreme of the data bus and the ddr(s) at the other extreme. other device(s) s hould be placed between the lpc3230 and ddr memory (closer to the ddr). 5. the pcb trace length of emc_dqs[1:0] should be at least 2 inches (but not more than 4 inches) longer than emc_dq[15: 0] and emc_dqm[1:0]. on a typical fr4 pcb this adds at least 334 p s to set-up time margin fo r ddr writes. for reads from ddr the increased trac e length of emc_dqs[1:0] will be automatically compensated for by the software initialization function find_ddr_dqsin_delay() which sets the optimal value ddr_dqsin_delay(sdramclk_ctrl[6:2]). the function find_ddr_dqsin_delay() can be found in the "ddr sdram setup code for the lpc32x0 series" on the nxp web site. example 128 mb system ddr sdram using a single emc_dycsx_n:
es_lpc3230 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 1 june 2011 10 of 17 nxp semiconductors es_lpc3230 errata sheet lpc3230 fig 5. 128 mb ddr sdram example 22ohms 22ohms 0.1uf 0.1uf 20kohms 1% 20kohms 1% v+_emc 22ohms 22ohms nc low byte high byte ba1:0 / a12:0 ncs cke, nras, ncas, nwe cke, nras, ncas, nwe ncs (64m x 8) (64m x 8) nclk vref clk ba1:0 / a12:0 dm dqs dq7:0 emc_clk_n emc_clk emc_control emc_dycs0_n emc_dqm1 emc_a[14:00] emc_d[07:00] emc_dqs0 emc_dqm0 dq7:0 dqs dm clk vref nclk lpc32x0 emc ddr emc_dqs1 emc_d[15:08] emc_clkin
es_lpc3230 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 1 june 2011 11 of 17 nxp semiconductors es_lpc3230 errata sheet lpc3230 3.4 ddr.1: ddr interface has >1.2 ns clock skew introduction: ddr memory uses a differential clock which is generated by the lpc3230. the differential clock consists of two clock si gnals: emc_clk is the positive clock and ddr_nclk is the negative clock. problem: there is approximately 1.27 ns of skew betw een the low transition of the ddr_nclk and the high transition of the emc_clk. this can cause two problems: 1) some ddr devices use this clock transition to drive a digital lock loop (dll) in the ddr device. the ddr clock skew can cause the ddr device's internal dll to loose lock, resulting in the wrong data being latched. 2) the ddr clock skew can also cause a reduced data valid window (also called data-out window) from a ddr device. however, the lpc3230 has a programmable dqs delay to achieve center alignment for accurate data reads. work-around: connecting the ddr device negative clock in put (ddr_nclk from the lpc3230) to the ddr reference voltage (vref - the midpoint of the ddr signal voltage swing, which is generally vddq/2) avoids the clock skew problem, though it also eliminates the advantages of differential signaling. the lpc3230 ddr_nclk output should be left unconnected. ddr reference voltage can be generated with a divide-by-two voltage divider. standard ddr memories usually requ ire a vref input, so this ddr reference voltage should already be available. mobile ddr devices typically do not have a vref input, so the external voltage divider may need to be added to the design for this work-around. it is also possible to compensate for the 1.27 ns clock skew by adding an additional 7 inches of pcb trace length to the emc_clk signal. however, this could have unintentional consequences; such as increased electro-magnetic interference. 3.5 lcd.1: low throughput when lcd controller accesses ddr/sdram introduction: the lcd controller is an ahb master that uses an internal dma controller to transfer frame data from memory to the lcd panel. problem: the time required to read data from either sdr or ddr sdram using the lcd dma controller takes longer than expected. this issue has little effe ct when the lcd dma controller reads frame data from iram or external sram. work-around: when using external sdram for the lcd framebuffer, use a display size and color depth that reserves sufficient system bandwidth for the remaining pe ripherals in the application. for systems using lcd displays sizes greater than qvga and high color we suggest the use of external sram.
es_lpc3230 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 1 june 2011 12 of 17 nxp semiconductors es_lpc3230 errata sheet lpc3230 3.6 rtc.1: an rtc match doesn?t drive the onsw pin active (high) introduction: an onsw output pin (m15) is included in the lpc3230 to assist in waking up the chip after power is removed from all functions except the rtc and battery ram. when there is an active match condition th e rtc will drive the onsw pin high. the rtc only drives the onsw pin while the match is active, and after 1 second of active match, if the software has not accessed the rtc block, the onsw pin will go low when the match is no longer active. problem: when power is removed from all functions except the rtc and battery ram, the rtc does not drive the onsw pin high when there is an active match condition. work-around: there is no work-around for this problem. 3.7 int.1: gpi_08 does not ge nerate an interrupt signal introduction: the lpc3230 contains 12 pins (gpi_00 - gp i_09, gpi_19, gpi_28 ) that function as dedicated general purpose inputs. each of thes e pins can generate an individual interrupt for the input pin. sub interrupt controlle r register 1 (sic1_er) and sub interrupt controller register 2 (sic2_er) contains bits that allow enabling or disabling the interrupt for the associated pin. problem: when bit nine is set to one in the sub interr upt controller 2 enable register (sic2_er[9]) it does not enable the interrupt for the gpi_08 pin. all other general purpose input pins (gpi_00 - gpi_07, gpi_09, gpi_19, gp i_28) interrupts work correctly. work-around: there is no work-around for this problem.
es_lpc3230 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 1 june 2011 13 of 17 nxp semiconductors es_lpc3230 errata sheet lpc3230 3.8 mcpwm.1: input pins (mci0-2) on the motor control pwm peripheral are not functional introduction: on the lpc3230, the motor control pwm (mcpwm) peripheral is optimized for three-phase ac and dc motor control applicatio ns and can also be used in applications which require timing, counting, capture, and comparison. the mcpwm contains three input pins (mci0-2) for pwm channels 0, 1, and 2. the inputs can be used as feedbacks for controlling brushless dc motors with hall s ensors, and also can be used to trigger a timer/counter?s (tc) capture or increment a channel?s tc when mcpwm is configured as a timer/counter. note: mci0-2 pins are also called mcfb0-2 (refer to lpc32x0 user manual for more details). problem: the input pins (mci0-2) are not functional. work-around: the gpio interrupts 1 need to be used instead of the mcpwm mci0-2 pins. on the lpc3230, the gpio interrupts can only be set to either trigger on the rising edge or on the falling edge. therefore, in or der to detect all six states of the connect ed hall sensor through an interrupt, the state of the pin needs to be determined and switch to rising or falling edge interrupt accordingly. 1. available gpio interrupt pins: gpio_00 to gpio_05, gpi_00 to gpi_09, gpi_19, gpi_28, and all port 0 and port 1 pins.
es_lpc3230 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 1 june 2011 14 of 17 nxp semiconductors es_lpc3230 errata sheet lpc3230 3.9 hsuart.1: high speed uart recei ve fifo and status can freeze introduction: the three high speed uart's (hsuart) rece ive (rx) fifos can sometimes enter a state where they no longer accept received data. when this state occurs, the hsuart's rx fifo will no longer accept data regardless of rx fifo fill st atus. the receive state of the hsuart may indicate a number of possible, but invalid, receive statuses. these invalid statuses may include rx fifo or timeout in terrupts pending with no receive data in the rx fifo, invalid rx fifo status, stuck rx interrupts, or other possible rx statuses. once the hsuart enters this state, the state can only be cleared by a chip reset. this applies to the u1_rx, u2_rx, and u7_rx pi ns. the hsuart's transmit side is not affected by this issue and will work as normal when the hsuart receive side stops. the four standard uarts do not exhibit this behavior. problem: it has been determined that this failed receive st ate can be entered by receiving a burst of high frequency noise into the hsuart rx pin. high frequency noise c onsists of pulsed or random toggling of the hsuart rx line at about 2.5 mhz or greater. the chance of the hsuart entering the state increases with the number of pulses and frequency of the pulses received. generally, a single pulse won't cause the state to occur. during normal data transfer with transfer rates 2400 bps (416 us) to 921.6 kbps (1.085 us), this state won't occur. however, conditions outside the transfer itself may cause the state to occur. it has been observed in some systems that insertion of the serial cable into the board's serial connector can cause connection noise or oscillations on the transceiver. this noise is driven onto the hsua rt rx pin from the transceiver as a series of random pulses. work-around: if all 7 uarts aren't needed or 921.6 kbps transfer rate isn't needed, use the standard uarts instead of the high speed uarts to avoid the issue altogether. for systems that require the hsuarts, care must be taken to limit the exposure of the hsuart rx signal for the type of signal conditions that can cause the state to occur. there are several possible solutions that can help reduce the state from occurring. whenever the hsuart is not in use, place the hsuart into loopback mode. when in loopback, the rx pin is connected internally to the hsuarts tx pin and is isolated from the external rx input. while in this loopback state, the condition won't occur on the hsuart regardless of the signal on the rx in put. the hsuart tx pin will remain in the idle state in loopback mode when no data is being sent from the hsuart. optionally, if the hsuart is connected to a transceiver that supports enabling and disabling of the input signal from the transceiver rx input to the tran sceiver rx output to the hsuart rx input, disable it when not expecting a transmission. regardless of how the transceiver is connected to the rx pin, the rx pin should be prevented from floating at power-up, reset, or when the transceiver is disabled. this can be done by adding a pull-up resistor to the hsuart rx pin. if using a system where the hsuart always need to be enabled, consider adding the capability to sense when the cable has been plugged into the conn ector and switch the hsuart out of loopback mode only once the cable has been installed to prevent cable insertion noise.
es_lpc3230 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 1 june 2011 15 of 17 nxp semiconductors es_lpc3230 errata sheet lpc3230 3.10 usb.1: usb host contro ller hangs on a dribble bit introduction: full-/low-speed signaling uses bit stuffing th roughout the packet without exception. if the receiver sees seven consecutive ones anywhere in the packet, then a bi t stuffing error has occurred and the packet should be ignored. the time interval just before an eop is a sp ecial case. the last data bit before the eop can become stretched by hub switching skews. this is known as dribble and can lead to a situation where dribble introduces a sixth bit that does not require a bit stuff. therefore, the receiver must accept a packet for which ther e are up to six full bit times at the port with no transitions prior to the eop. problem: the usb host controller will hang indefinitely if it sees a dri bble bit on the usb bus. it will hang the first time a dribble bit is seen. once it is in this state there is no recovery other than a hard chip reset. this problem has no effect on the usb device controller. work-around: none. 4. ac/dc deviations detail 4.1 esd.1: weak esd prot ection on reset_n pad introduction: the lpc3230 was designed to withstand electrostatic discharges up to 2000 v using the human body model. problem: the reset_n pad (pin m14) does not pass esd tests above 1000 v. work-around: observe proper esd handling precautions for the reset_n pin
es_lpc3230 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 1 june 2011 16 of 17 nxp semiconductors es_lpc3230 errata sheet lpc3230 5. legal information 5.1 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. 5.2 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 5.3 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners.
nxp semiconductors es_lpc3230 errata sheet lpc3230 ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 1 june 2011 document identifier: es_lpc3230 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 6. contents 1 product identification . . . . . . . . . . . . . . . . . . . . 3 2 errata overview . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 functional problems detail . . . . . . . . . . . . . . . . 5 3.1 dma.1: single burst dma memory-to-memory transfers have additional memory cycles when the dma source memory is on the emc bus . . . . . 5 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.2 nor.1: when booting from nor flash, sdram devices will not release the data bus, preventing the lpc3230 from booting correctly . . . . . . . . . 7 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.3 ddr.2: ddr emc_d[15:0] to emc_dqs[1:0] data output set-up time, t su(q) , for mcu write to ddr provides limited timing margin . . . . . . . . . 8 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4 ddr.1: ddr interface has >1.2 ns clock skew 11 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .11 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.5 lcd.1: low throughput when lcd controller accesses ddr/sdram . . . . . . . . . . . . . . . . . 11 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .11 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.6 rtc.1: an rtc match doesn?t drive the onsw pin active (high) . . . . . . . . . . . . . . . . . . . . . . 12 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .12 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.7 int.1: gpi_08 does not generate an interrupt signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .12 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.8 mcpwm.1: input pins (mci0-2) on the motor control pwm peripheral are not functional. . . 13 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .13 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.9 hsuart.1: high speed uart receive fifo and status can freeze . . . . . . . . . . . . . . . . . . . . . . 14 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .14 problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.10 usb.1: usb host controller hangs on a dribble bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 ac/dc deviations detail . . . . . . . . . . . . . . . . . 15 4.1 esd.1: weak esd protection on reset_n pad 15 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 legal information . . . . . . . . . . . . . . . . . . . . . . 16 5.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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